Lab 3: Adders

Orientation

Build the same full adder two ways

Need a refresher?
→ Creating a Quartus Prime Project · → DE0-Nano FPGA

Analysis

Complete the full-adder truth table

A full adder combines two input bits and an incoming carry. For each row, determine the output bit S and the carry passed to the next position, Cout. Complete all eight rows before moving on.

Enter only 0 or 1. Type one binary digit in each S and Cout box.

Need a refresher?
→ Truth Tables · → Binary Addition

Analysis

Derive and simplify the output functions

Use your completed truth table to write a Boolean function for each output. Show the terms you obtain from the applicable rows, then simplify using the method taught in class. Keep your handwritten derivation with your circuit diagram.

Need a refresher?
→ Boolean Expressions from Truth Tables · → Boolean Simplification

Structural modelling

Draw, check, and show the gate-level circuit

Translate both simplified functions into a gate-level circuit. Make the inputs A, B, and Cin and the outputs S and Cout clear. Check that the connections represent your expressions before opening Quartus.

1. Draw the complete structural circuit using the required gates and labelled nets.
2. Trace at least two different truth-table rows through the circuit to check both outputs.
3. Show the truth table, function simplification, and circuit diagram to your lab instructor before FPGA implementation.

Need a refresher?
→ Structural Logic Design

Quartus schematic

Implement the structural circuit

1. Create a new Quartus Prime project for the full-adder schematic using the established Lab 2 project workflow.
2. Create a Block Diagram/Schematic File, place the gates required by your design, wire them, and name A, B, Cin, S, and Cout.
3. Compile the design and resolve reported errors before assigning I/O.
4. In Pin Planner, connect A, B, and Cin to the DE0-Nano DIP switches. Connect S to LED0 and Cout to LED1.

Need a refresher?
→ Block Diagram/Schematic Files · → Pin Planner

Physical verification

Program and test the structural design

Program the DE0-Nano using the established Lab 2 workflow. Test every input combination, not just a convenient example. The LEDs must match the truth table you completed.

Need a refresher?
→ FPGA Programming

Behavioral modelling

Describe the same full-adder behaviour in Verilog

You have implemented an explicit gate network. Now use Verilog to describe the full-adder’s behaviour so that synthesis can produce equivalent logic. Start a new project and a new Verilog file, then use the supplied module structure.

module full_adder(A, B, Cin, S, Cout);
  input A, B, Cin;
  output S, Cout;

  assign {Cout, S} = A + B + Cin;
endmodule

Reading the assignment: braces concatenate the two output bits so the arithmetic result’s high bit becomes Cout and low bit becomes S. This is a behavioral description, not a sequence of software statements.

1. Save the Verilog file and set the correct top-level entity.
2. Compile, synthesize, assign the same inputs and outputs, and program the FPGA using the Lab 2 workflow.
3. Keep the final .v source file for the local ZIP.

Need a refresher?
→ Verilog Modules and Ports

Physical verification

Compile, program, and verify the behavioral design

Compile and program the behavioral design, then test all eight DIP-switch combinations. The physical outputs should agree with the structural full adder because both designs describe the same required behaviour.

Comparison

Compare the two design approaches

Both implementations are intended to create the same input/output behaviour. Compare what each representation makes visible and what it leaves to synthesis.

Think it through

Connect the reasoning to the hardware

Completion

Prepare your Lab 3 completion package