Lab 5: Elevator Floor Display Circuit

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Orientation

Build a two-floor display from physical logic

Objective

Test a common-anode seven-segment display, control it with an SN74LS47 BCD decoder/driver, and design NAND/NOT logic that converts two elevator pushbuttons into the BCD inputs for floors 1 and 2.

Character test

Verify all seven segments, then form the character L.

BCD verification

Display and record decimal digits 0 through 9.

Elevator interface

Derive, build, and demonstrate two floor-button states.

Power OFF before wiring.

Remove bench power before adding, removing, or moving IC, display, resistor, pushbutton, or jumper connections. Set the supply to 5 V with a protective current limit while disconnected, and obtain the required instructor check before first power-up.

Required materials
Part	Quantity	Role
SN74LS47	1	BCD-to-seven-segment decoder/driver
CD74HC05E	1	Six open-drain inverters
SN74LS20	2	Four total 4-input NAND gates
INND-TS40RAB	1	Common-anode red seven-segment display
220 Ω resistors	7	One current limiter per segment
100 Ω resistors	3 provided; 1 used	Common-anode protection connection shown in the display circuits
1 kΩ pull-up resistors	4	Two pushbutton nodes and two used HC05 outputs
Pushbuttons	4 provided; 2 used	Floor 1 and Floor 2 commands
Breadboard and jumper wires	1 set	Physical construction

I have identified the listed parts, datasheets, breadboard, and current-limited 5 V bench supply.

Component preparation

Read the package before placing the part

For every DIP IC, find the notch or dot, identify Pin 1, and count pins counter-clockwise when viewed from above. Place each IC across the breadboard centre channel. Verify the exact marking before using a pin diagram.

Verified component behavior
Part	Supply and package	Behavior needed here
SN74LS47N	16-pin PDIP; Pin 16 VCC, Pin 8 GND; 4.75–5.25 V	BCD A–D inputs; active-LOW open-collector segment outputs a–g; LT, RBI, and BI/RBO controls
CD74HC05E	14-pin PDIP; Pin 14 VCC, Pin 7 GND; operate at 5 V here	Six inverters with open-drain outputs. Every used output requires a pull-up; unused inputs must be tied to a defined level.
SN74LS20N	14-pin PDIP; Pin 14 VCC, Pin 7 GND; 4.75–5.25 V	Two independent 4-input positive-NAND gates. Every input of a used gate must be defined.
INND-TS40RAB	10-lead through-hole display; common anode at Pin 6; Pin 4 has no connection	Segment pins: a=10, b=9, c=8, d=5, e=1, f=2, g=3, decimal point=7

SN74LS47 display-driver datasheet table highlighting the INND-TS40RXX red display row and its 70 mW power rating, 25 mA current, and 5 V rating — Datasheet reference for the red INND-TS40 display ratings. Treat these as limits, not target operating values.

Common-anode INND-TS40 display diagram identifying segments a through g, decimal point, common-anode Pin 6, segment pin numbers, and unused Pin 4 — Seven-segment display segment naming and pin identification

Top-view SN74LS47 16-pin package pinout showing B, C, lamp test, blanking controls, D, A, ground, segment outputs e through f, and VCC — SN74LS47 top-view pin identification

Interface constraint

A 74LS output HIGH is not guaranteed to reach the 3.15 V HIGH threshold of a 5 V HC input. Do not route an SN74LS20 output directly into a CD74HC05E input. A pulled-up HC05 output can feed an LS20 input.

Need a refresher?
→ Reading Digital-IC Datasheets · → TTL and CMOS Logic Families

SN74LS47 typical supply voltage (V) SN74LS47 recommended maximum on-state segment-output current per output (mA) What useful test does the active-LOW LT input provide? I verified each physical marking, notch/Pin 1, power pins, used signal pins, and unused-input plan against the approved datasheet.

Display subsystem

Test every segment before adding logic

Five-volt common-anode seven-segment test circuit with common anode connected through 100 ohms to 5 volts and seven separate 220 ohm segment resistors connected to ground — Seven-segment display test circuit

Power off: place the display and confirm its orientation. Connect common-anode Pin 6 to +5 V through the 100 Ω protection resistor shown.
Connect each segment pin a–g through its own 220 Ω resistor to ground. Leave decimal-point Pin 7 disconnected.
Ask the instructor/TA to inspect the display orientation, resistor placement, +5 V rail, and ground rail. Record the check below before applying power.
Apply the current-limited 5 V supply. Confirm that all seven segments illuminate.
With power off between changes, disconnect the segment resistors that are not needed to form the character L. Reapply power and observe the result.

Why LOW turns a segment on

The display’s segment anodes share +5 V. Current flows only when a segment cathode has a path toward ground. Grounding that cathode through its resistor therefore illuminates the segment.

My instructor or TA checked the display test wiring before I applied power.This records your action; the browser does not grant approval.

Need a refresher?
→ Seven-Segment Displays

Decoder subsystem

Wire the SN74LS47 to the common-anode display

Five-volt SN74LS47 BCD decoder connected through seven individual 220 ohm resistors to a common-anode seven-segment display — BCD decoder/driver and common-anode display circuit

Power off: insert the SN74LS47 across the centre channel. Connect Pin 16 to +5 V and Pin 8 to ground.
For normal display operation, hold LT (Pin 3), BI/RBO (Pin 4), and RBI (Pin 5) HIGH at +5 V. Do not leave control inputs floating.
Connect outputs a–g to the matching display segment pins through seven separate 220 Ω resistors: a Pin 13, b Pin 12, c Pin 11, d Pin 10, e Pin 9, f Pin 15, g Pin 14.
Connect display common-anode Pin 6 to +5 V. Keep the decimal point disconnected.
Initially connect B (Pin 1), C (Pin 2), D (Pin 6), and A (Pin 7) to ground for BCD 0000.
Obtain an instructor/TA wiring check, apply the current-limited 5 V supply, and confirm digit 0.

Current path: +5 V enters the common anode, passes through an illuminated LED segment and its 220 Ω resistor, then enters an active-LOW SN74LS47 open-collector output that sinks current to ground.

My instructor or TA checked my wiring before I turned on the 5 V supply. What digit do you see when BCD is 0000?

Need a refresher?
→ BCD-to-Seven-Segment Decoder/Drivers · → Open-Collector and Open-Drain Outputs

BCD verification

Display decimal digits 0 through 9

Work one row at a time. Turn the power off before changing wires. Set the four inputs D, C, B, and A, then type those four switch values in the second column. Turn the power on, look at the seven-segment display, and type the digit you see in the third column.

How to use this chart:

The number on the left is the digit you are testing. In the second column, type the four switch values you used, in the order D C B A. In the third column, type the digit that actually appears on the display. The last column reports whether both entries are correct.

Enter your switch settings and the digit you see
Digit to test	Your D C B A settings	Digit shown on display	Check
0
1
2
3
4
5
6
7
8
9

Scope: codes 1010 through 1111 are not valid single-digit BCD. Do not depend on a particular displayed result for those codes in this experiment.

Upload three display photos:

Take one clear photo while the display shows 0, one while it shows 5, and one while it shows 9. Each photo should show the lit digit and enough of the decoder/display wiring to identify the circuit. Select the three image files below; they are added to the local ZIP and are not submitted to Avenue automatically.

Photo showing digit 0No file selected.Any image format is accepted. Upload a clear photo showing the display lit as 0. Photo showing digit 5No file selected.Any image format is accepted. Upload a clear photo showing the display lit as 5. Photo showing digit 9No file selected.Any image format is accepted. Upload a clear photo showing the display lit as 9. I demonstrated the verified BCD digits to my instructor or TA.

Need a refresher?
→ Binary-Coded Decimal

Input subsystem

Build and test two active-LOW pushbuttons

Pushbutton input circuit with a 1 kilohm pull-up resistor from 5 volts to Vout and a normally-open pushbutton from Vout to ground — Defined pushbutton input using a 1 kΩ pull-up

Power off: build two copies, labelled Floor 1 and Floor 2. Each output node connects through 1 kΩ to +5 V and through its pushbutton to ground.
Check pushbutton terminal pairs with continuity while power is off; four-pin tactile switches often connect same-side pins internally.
Apply 5 V and measure each output relative to circuit ground when released and pressed.
Remove power before connecting these outputs to IC inputs.

What to record:

Measure the button output voltage with your multimeter. Record one reading while both buttons are released, then record one reading while the button you are testing is pressed. “Released” means no button is being pressed. “Pressed” means the selected button is held down. Keep the black meter lead connected to circuit ground.

Floor 1 & Floor 2 released voltage (V)Floor 1 & Floor 2 pressed voltage (V)

Button polarity Why is the pull-up resistor required?

Logic design

Derive the two-floor encoder

Design combinational logic that produces BCD 0001 when only Floor 1 is pressed and BCD 0010 when only Floor 2 is pressed. Connect BCD_C and BCD_D permanently to ground. Treat neither-button and both-button states as invalid commands: your design must produce a defined output, and you must document the chosen behavior.

Elevator logic requirements
Floor 1 button	Floor 2 button	Meaning	Required/defined BCD output
Released	Released	No request
Pressed	Released	Floor 1	`0001`
Released	Pressed	Floor 2	`0010`
Pressed	Pressed	Conflicting request

Implementation constraints

Use the available CD74HC05E NOT gates and SN74LS20 4-input NAND gates.
Add a 1 kΩ pull-up from +5 V to every used HC05 open-drain output.
Do not drive an HC05 input from an LS20 output. Arrange the design so HC05 outputs feed LS20 inputs; use a NAND gate with all inputs joined when an LS-family inversion is needed.
Tie unused HC05 inputs to ground. Tie every unused input of each used SN74LS20 gate to a defined HIGH or LOW as required by your expression.

Boolean expression for BCD_A Boolean expression for BCD_B Describe your defined behavior for no request and simultaneous requests. Elevator logic schematicNo file selected.Select a clear image or PDF showing the button signals, gate pin numbers, pull-ups, BCD_A/BCD_B, +5 V, and ground. The assessed Boolean solution belongs in your evidence, not in the refresher topics. I showed my completed logic schematic and interface plan to my instructor or TA.

Need refreshers?
→ Boolean Simplification · → Basic Logic Gates

Physical integration

Build the NAND/NOT logic and connect the decoder

Power off: place one CD74HC05E and both SN74LS20 ICs across the centre channel with aligned notch orientation.
Connect Pin 14 of each 14-pin IC to +5 V and Pin 7 to ground. Keep the SN74LS47 at the same +5 V/common-ground rails.
Wire your reviewed logic schematic using verified gate pinouts. Install each required open-drain pull-up before connecting the next stage.
Connect the logic outputs to SN74LS47 BCD_A (Pin 7) and BCD_B (Pin 1). Tie BCD_C (Pin 2) and BCD_D (Pin 6) to ground.
Audit every IC input: each must trace to +5 V, ground, a pull-up-defined button node, or a driven logic output. No input may float.
Ask the instructor/TA to inspect orientation, rails, pull-ups, family direction, decoder controls, segment resistors, and the complete point-to-point schematic comparison before power-up.

Final power audit
Device	+5 V	Ground	Other required defined nodes
SN74LS47	Pin 16	Pin 8	LT, BI/RBO, RBI HIGH; A–D defined
CD74HC05E	Pin 14	Pin 7	Used outputs pulled up; unused inputs grounded
Each SN74LS20	Pin 14	Pin 7	Every gate input defined
INND-TS40RAB	Common anode Pin 6	Through active segment paths	One 220 Ω resistor per segment

My instructor or TA checked the completed, unpowered circuit before I applied 5 V.

System verification

Test every elevator-button state

Apply the current-limited 5 V supply and test systematically. Record logic voltages with respect to circuit ground and the actual displayed result. Do not change wiring while powered.

Elevator floor-display verification
Floor 1	Floor 2	BCD_B (V)	BCD_A (V)	Observed display	Matches design?
Released	Released
Pressed	Released
Released	Pressed
Pressed	Pressed

Completed elevator display circuitNo file selected.Capture the full breadboard so the IC markings/orientation, display, power rails, pushbuttons, pull-ups, segment resistors, and main interconnections are visible. Include a correct floor display state; do not include faces. I demonstrated both floor requests and the defined no-request/conflict behaviour to my instructor or TA.

Think it through

Explain the completed circuit

Why does an active-LOW SN74LS47 segment output illuminate a segment in this common-anode display? Why would a floating pushbutton, decoder-control, NAND, or inverter input make the displayed result unreliable? How is BCD different from treating an entire multi-digit decimal value as one ordinary binary number, and what work does the SN74LS47 save? Explain one design choice that keeps the SN74LS20/CD74HC05E interface within guaranteed logic levels.

Completion

Prepare the Lab 5 submission

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I reviewed component identification, BCD table, derivation, wiring checks, all four button states, evidence, answers, and demonstrations.

Submission package

Download your Lab 5 submission ZIP

The ZIP includes completion.json, BCD display evidence, your logic schematic, and the completed-circuit evidence selected in this browser session.

Submission Details

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Student NamesStudent NumbersLab SectionLab Instructor

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