Lab 7: Four-Bit Gray Counter

Orientation

Build a counter whose adjacent words differ by one bit

Objective

Apply your Verilog and sequential-logic skills to design the required four-bit reflected Gray counter. Advance it manually, verify all 16 states and the return to state 0, then demonstrate and explain the design.

Required resources
Resource	Requirement
DE0-Nano	One board and USB-Blaster connection
Quartus Prime	25.1 Lite Edition with Cyclone IV device support
Reference	DE0-Nano User Manual, version 1.9

Board care

This activity uses onboard switches and LEDs only. Keep the board on a non-conductive surface, confirm the target device and assignments before programming, and disconnect power before attaching or removing external hardware.

Need a refresher?
→ Gray Code

I have the DE0-Nano, Quartus Prime, and the board manual available.

Required sequence

Record the 16-state reflected Gray sequence

Enter four bits for each regular count. Use B3 as the most-significant bit and B0 as the least-significant bit. Your sequence must begin at 0000, follow the specified reflected ordering, and return from state 15 to state 0 with only one bit changing.

Gray-counter design table
State	Regular count	Gray word B3B2B1B0	Check
0	0000
1	0001
2	0010
3	0011
4	0100
5	0101
6	0110
7	0111
8	1000
9	1001
10	1010
11	1011
12	1100
13	1101
14	1110
15	1111

Complete all 16 words to check the sequence.

Design plan

Separate state from displayed code

Use a four-bit register to hold the regular count and give it an explicit power-up value of zero.
Increment that register on the positive edge of the manual advance input. Four-bit overflow returns 1111 to 0000.
Translate the regular count into the required Gray word with combinational logic.
Drive LED3 through LED0 from B3 through B0.

No reset input is required.

The design starts at state 0 through an explicit register initialization supported by the Quartus/Cyclone configuration flow. Do not add an unassigned reset port.

Need refreshers?
→ Combinational vs Sequential Logic · → Clock Signals and Active Edges

State-update planOutput-translation plan

Verilog

Implement your design

Create a Quartus project targeting EP4CE22F17C6.
Create one Verilog source file and keep its module name consistent with the project top-level entity.
Declare one manual-advance input and outputs LED3 through LED0.
Implement the registered count and combinational Gray translation from your plan.
Run Analysis & Synthesis. Resolve errors and inspect warnings before assigning pins.

This lab intentionally does not provide completed starter code. Your source file is the assessed design, and you must be able to explain it.

Need refreshers?
→ Verilog Modules and Ports · → Combinational Logic in Verilog

Synthesis checkFinal Verilog source (.v)Select the final source file that you will explain to the instructor.

Compile and program

Assign SW0 and the four LEDs

DE0-Nano assignments for this design
HDL function	Board resource	Location	Behavior
Manual advance	SW0	PIN_M1	LOW in upper position; HIGH in down position
Gray B3	LED3	PIN_A11	Most-significant displayed bit
Gray B2	LED2	PIN_B13	Displayed bit
Gray B1	LED1	PIN_A13	Displayed bit
Gray B0	LED0	PIN_A15	Least-significant displayed bit

In Pin Planner, assign your advance port to SW0 and the outputs to LED3–LED0 as listed.
Compile the complete design and confirm the assignments remain present.
Connect USB-Blaster, open Programmer in JTAG mode, and program the generated .sof.
Place SW0 in the upper position before beginning the controlled test.

SW0 is a slide switch, not a debounced pushbutton.

A positive edge occurs when SW0 moves from upper (LOW) to down (HIGH). Return it to upper to prepare the next positive edge. Mechanical contact bounce can create extra transitions, so move deliberately and record any skipped state rather than assuming every movement creates one ideal edge.

Need refreshers?
→ Pin Planner · → Programming the FPGA

Programming check

Verify the full cycle

Observe every state and the wraparound

Record the initial LED3–LED0 word before the first positive edge.
For each next row, move SW0 from upper to down, read the LEDs, then return SW0 to upper.
Continue through all 16 states, then create one more positive edge and confirm the display returns to state 0.

Observed LED sequence
State	Observed LED3LED2LED1LED0	Check
0 (initial)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Next edge

Complete every observation to check the physical sequence.

Programmed-board evidenceSelect one clear image or PDF that identifies the programmed board and shows a meaningful Gray-counter result.

Physical behavior

Demonstrate and explain the implementation

Manual-switch observationInstructor demonstrationCode explanation

Analyze

Think it through

How does your observation table demonstrate the defining one-bit-change property of this Gray sequence, including the transition from state 15 back to state 0?Why keep a regular binary count as state and derive the Gray outputs, instead of updating four Gray bits as independent state?Why can a mechanical switch produce more than one count for a single movement, and what kind of input-conditioning strategy would make manual advancement reliable?

Completion

Prepare your Lab 7 submission package

Assessment distinction

Complete and export this HTML record, select files for the local ZIP, demonstrate the working counter to the instructor, and explain your code. Creating the ZIP does not perform the instructor demonstration or submit anything to Avenue.

Final review

Submission package

Download your Lab 7 submission ZIP

The ZIP includes completion.json, the final Verilog source, and programmed-board evidence.

Submission Details

Enter all four required details before downloading.

Student NamesStudent NumbersLab SectionLab Instructor

Generating this local ZIP does not submit work. Evidence files must be reselected after reopening the page.