Lab 8: Sequential Christmas-Light Controller

Orientation

Translate a lighting specification into sequential hardware

Design objective

Use the DE0-Nano onboard clock, reusable Verilog modules, and a finite state machine to control three two-colour bulbs. Each bulb contains one red LED and one blue LED; energizing both produces purple light.

Required pattern

On reset, bulb 1 is red for 1 second.
Bulb 1 turns off; bulb 2 is purple for 1 second.
Bulb 2 turns off; bulb 3 is blue for 1 second.
Bulb 3 becomes red for 1 second.
Bulb 3 turns off; bulb 2 is purple for 1 second.
The cycle repeats with bulb 1 red.

Required resources
Resource	Quantity
DE0-Nano and USB-Blaster connection	1
Quartus Prime 25.1 Lite	1
External LEDs: three red and three blue	6
220 Ω resistors	6
Breadboard and jumper wires	As required
DE0-Nano User Manual	Version 1.9 or later board-equivalent reference

External-circuit safety

Disconnect board power before wiring or changing connections. Give every LED its own 220 Ω series resistor, verify LED polarity, use only the listed 3.3 V GPIO signals, and connect the circuit ground to a DE0-Nano GPIO-header GND pin. Inspect for shorts before powering the board.

Need a refresher?
→ Finite State Machines

I have the board, six LEDs, six 220-ohm resistors, breadboard, jumpers, and board reference.

States and sequence

Convert the specification into a complete state table

Choose five unique state names. For each step, enter the present state, the next state, six active-HIGH LED outputs, and the state duration. The next state in the final row must return to the state named in the first row.

Student-designed state table
Step	Present state	Next state	B1 red	B1 blue	B2 red	B2 blue	B3 red	B3 blue	Duration (s)	Check
1
2			Six-bit active-HIGH output word: B1R B1B B2R B2B B3R B3B
3
4
5

Complete all five rows to validate the external sequence.

State diagram or equivalent design planSelect one readable image or PDF showing all five states, transitions, reset entry, outputs, and cyclic return.

Timing

Derive a one-second state-enable pulse

Keep the FSM on CLOCK_50 and generate a one-cycle enable pulse at each one-second boundary. For the specified zero-based counter formulation, count from zero through the terminal value inclusive, assert the enable, and clear the counter on that same rising edge.

Base clock frequency (Hz)Base-clock cycles per stateZero-based terminal countMinimum counter width (bits)

Timing implementation check

Need a refresher?
→ Clock Signals and Active Edges · → Binary Counters as Frequency Dividers

FSM design

Define the controller architecture

KEY0 resets the timing counter and controller to the first lighting state.
The state register changes only on a rising CLOCK_50 edge when the one-second enable is asserted.
All six active-HIGH outputs are fully defined for every legal state.
Provide deterministic recovery to the reset state for an unexpected encoding.
Do not assume a particular binary, one-hot, or Gray encoding unless you choose it and can justify it.

FSM implementation style and encodingModule decomposition and port connectionsReset and illegal-state recovery plan

Need a refresher?
→ Finite State Machines · → Verilog Modules and Ports

Verilog

Implement the timing, controller, and integration

Write synthesizable Verilog from your state diagram and timing plan. Use nonblocking assignments for clocked state. If you use combinational procedural logic, give next-state and output signals complete assignments so no latch is inferred. Do not use simulation delays, forever, or repeat.

Implement the one-second enable logic.
Implement the five-state controller and six outputs.
Integrate the modules under one top-level entity with CLOCK_50, KEY0, and the six LED ports.
Analyze and synthesize; inspect warnings and the inferred state machine before compilation.

Need a refresher?
→ Combinational Logic in Verilog

Synthesis reviewComplete Verilog source (.v)Select the final student-authored .v file containing every module required to rebuild the design.

Build and program

Wire, assign, compile, and program

Verified physical I/O contract
Function	Board signal	FPGA location	Polarity
50 MHz clock	CLOCK_50	PIN_R8	Rising-edge clock
Reset	KEY0	PIN_J15	Active LOW when pressed
Bulb 1 red	GPIO_00	PIN_D3	Active HIGH
Bulb 1 blue	GPIO_01	PIN_C3	Active HIGH
Bulb 2 red	GPIO_02	PIN_A2	Active HIGH
Bulb 2 blue	GPIO_03	PIN_A3	Active HIGH
Bulb 3 red	GPIO_04	PIN_B3	Active HIGH
Bulb 3 blue	GPIO_05	PIN_B4	Active HIGH

Wire each channel identically

GPIO output → 220 Ω resistor → LED anode; LED cathode → common GND. Labels identify red and blue channels; colour is never the only identifier.

With power disconnected, build and inspect all six current-limited LED channels.
Apply the listed Pin Planner assignments using 3.3-V LVTTL.
Compile the design, program the generated .sof, then press KEY0 to establish the first state.

Need refreshers?
→ Pin Planner · → Programming the FPGA

Build check

Verify

Observe the full physical cycle and timing

Press and release KEY0, then observe at least one complete five-state cycle and the return to the first state. Record what the hardware actually does; do not infer observations from the code.

Physical verification record
Step	Observed active LEDs	Measured/observed duration (s)	Matches planned state?
1 after reset
2
3
4
5

Reset and cyclic-return observationProgrammed-lighting evidenceSelect one clear image or PDF identifying the external three-bulb assembly and a meaningful programmed state.Instructor demonstrationCode explanation

Why does this controller need stored state even though the output pattern is fixed?How do 50,000,000 base-clock cycles produce each one-second state interval, and what off-by-one error would result from counting zero through 50,000,000 inclusive?Why are the two purple appearances separate states even though their six output values are identical?

Completion

Prepare your Lab 8 submission package

Assessment distinction

Complete and export this HTML record, select the design and source files for the local ZIP, demonstrate the physical sequence to the instructor, and explain your code. Creating the ZIP does not perform the demonstration or submit anything to Avenue.

Final review

Submission package

Download your Lab 8 submission ZIP

The ZIP includes completion.json, the state-design evidence, complete Verilog source, and programmed-lighting evidence.

Submission Details

Enter all four required details before downloading.

Student NamesStudent NumbersLab SectionLab Instructor

Generating this local ZIP does not submit work. Evidence files must be reselected after reopening the page.