SMRTTECH 3DE3 - Digital Electronics
Interactive digital-electronics laboratory manuals and a shared Skill Tree in one student space, connecting physical builds, FPGA design, measurements, and reusable concepts.
System Architecture
The course hub routes students into each interactive manual, each lab links to the shared Skill Tree when a refresher is useful, and project work remains separate from numbered-lab progress.
Start page, lab catalog, architecture overview, and student orientation.
Interactive stages, measurements, checks, evidence capture, and local completion records.
Short reusable articles for circuits, FPGA design, Verilog, instruments, and troubleshooting.
McMaster styling, diagrams, lab figures, source references, and course-owned media.
The course project extends the same shell without being labelled as Lab 9.
Information Model
Procedures, stages, tables, quizzes, and checklists.
Reusable explanations independent of a single lab.
Local student entries, measurements, predictions, and reflections.
Implementation Model
The portal runs as a static site, keeps student work in the browser, and isolates 3DE3 lab and project records from other courses.
View the lab catalogLaboratory Catalog
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Build an inverting BC547 transistor switch, measure its transfer characteristic, and investigate switching time.
AvailableImplement and verify schematic and Verilog combinational logic on the DE0-Nano FPGA.
AvailableDerive, implement, and verify a full adder as both a schematic and behavioral Verilog design.
AvailableCombine a counter, multiplexer, and decoder as reusable FPGA design blocks.
AvailableBuild and verify a physical BCD-to-seven-segment elevator display using pushbuttons and logic ICs.
AvailableUse counters and D flip-flops to divide the DE0-Nano clock and investigate duty-cycle-controlled LED brightness.
AvailableDesign and verify a complete reflected Gray-code sequence in Verilog on the DE0-Nano.
AvailableDesign a timed five-state controller for six external red and blue LEDs.
Final ProjectDesign, integrate, demonstrate, and document a three-floor elevator controller using digital ICs, an FPGA, or a justified hybrid approach.
Browser data
This clears saved 3DE3 lab progress, answers, stage confirmations, cached filenames, and completion details from this browser. It does not delete files on your computer or change submitted work.
Shared Skill Tree
The Skill Tree provides reusable foundations for circuits, measurements, digital logic, FPGA design, Verilog, instruments, and troubleshooting. Contextual links return students to the originating lab.
Student Experience
The architecture supports students who get stuck: each concept has a short explanation and a relevant lab connection instead of forcing students to search through PDFs.
Open safe bench practice